The present invention relates to data transfer apparatus for use in data processing systems and, more particularly, to a controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for reliability independent of the peripheral storage device.
Data processing systems comprising a CPU, a peripheral storage device, such as a disk system, and a controller for interfacing the CPU to the peripheral storage device are well known in the art. The controllers employed in these systems usually include a sequencer for controlling the flow of data to and from the peripheral storage device, a buffer for providing temporary storage of data being transferred to and from the CPU and a microprocessor for controlling the operations of the sequencer, the buffer and other logic, such as error detection circuits.
During a write operation, data is transferred from the CPU to the sequencer through the buffer and then from the sequencer to the peripheral storage device. During a read operation, data is transferred from the peripheral storage device to the sequencer and then from the sequencer to the CPU through the buffer.
In the past, the operation of such data processing systems has been tested in two stages. First the CPU is tested apart from the remainder of the system to insure that it is functioning properly. Then, the controller and peripheral storage device are tested as a subsystem to determine if those two units in combination are functioning properly. In both stages, the testing is accomplished through the use of diagnostic programs. In testing the operation of the controller and peripheral storage device as a subsystem, special test words are sent from the CPU through the controller to the peripheral storage device and then sent back from the peripheral storage device to the CPU through the controller. A comparison is then made of the words sent and the words retrieved. If they are identical it is assumed that the subsystem is functioning properly. If they are not identical a malfunction is present somewhere in the subsystem.
Although this technique for testing the overall system has proven to be generally satisfactory for detecting malfunctions in the CPU, it has not proven to be totally adequate or acceptable for testing the operation of the remainder of the system.
One of the shortcomings with the technique is that it only reveals if the controller and peripheral storage device as a subsystem are functioning properly. If a malfunction is indicated, it does not reveal whether the malfunction is in the controller or in the peripheral storage device. Another shortcoming with the technique is that it does not test the operation of the controller in a complete manner. The test only makes a comparison of a word read back to the CPU with a word written into the peripheral storage device. The technique does not involve forcing or creating improper operations in the subsystem and consequently is not conclusive as to whether the error detection logic and other circuits and parts in the controller or peripheral storage device are functioning properly.
Accordingly, the need exists for a controller for interfacing a CPU with a peripheral storage device which can be tested for proper operation apart from the peripheral storage device and which can be tested in a more complete manner than in the prior art.